Hyper… What?
Block Diagram
Registers
Core Architecture Highlights
Instruction Set
Entry Tables
- TRAP Instructions
- Floating Point Instruction Emulation
Arcade Platforms
Games

Hyper… What?

The Hyperstone E1 microprocessors (E1-16 and E1-32), developed in the 90s in Konstanz, Germany, showed an interesting idea of embedded systems. They combined a fast RISC-style CPU with extra DSP instructions and built-in microcontroller features. Hyperstone was not as popular as ARM, PPC, MIPS or x86, but it was made for stable and predictable performance, good for industrial and storage use. The older E1-16 used a 16-bit architecture. It was quite simple and worked well, but had limits in address space and newer instruction features. The E1-32 was more advanced, using 32-bit design. It gave better speed, more flexible memory access, and stronger support for real-time tasks. It was not pure RISC, but had some similar ideas - like load/store model, and also added custom parts for I/O and DSP-style operations.

Hyperstone CPUs are very niche and almost unknown on the market. They were produced or licensed by Hyperstone and Hynix (models like GMS30C2116 and GMS30C2132). There is also some info about a Zilog device (Z32H00) based on Hyperstone, but not much is available about it.

Interestingly, around late 1990s and early 2000s, in South Korea (and only there), few dozen arcade machines were made using Hyperstone E1 CPUs (both 16 and 32-bit). These used different hardware setups -various video and sound chips etc. I was involved in emulating these games (and writing CPU core), that’s why i wrote this article and got interested in Hyperstone. Description of arcade platforms and games running on them is below.

Block Diagram

X - First operand (input) - register or path, used for ALU operations, memory access, etc.
Y - Second operand (input) - register or path, often paired with X for binary operations.
I - Immediate value or third operand, used for constants or offset values in instructions.
Z - Destination register or result path used to store the result of ALU / DSP operations.
W - Write-back operand or secondary destination. May be used for memory store or dual-result instructions.
A - Address operand or pointer, used in load/store instructions to calculate memory addresses.
PC - Program Counter.

The block diagram show internal structure of Hyperstone CPU. It use register-based architecture with separate paths for X, Y, Z operands and I for immediate values. Instruction cache connect to decode units which split instruction into control and operand signals. Execution unit include ALU, barrel shifter and DSP logic, working on X and Y inputs and write result to Z. Memory access pipeline handle load/store operations with address calculated from A path. Bus interface manage external communication. All components are connected with control and data buses, optimized for fast execution and low latency. Other parts not shown in the diagram include watchdog, timers, and PLL control to keep system stable. There is also internal RAM inside the Hyperstone CPU (size depends on model, usually few kilobytes). It helps with fast access and reduces need for external memory in small systems.

Registers

The E1-32X uses a split register model:

Global Registers: These are always accessible, kinda like your standard general-purpose registers. They’re used for things like passing parameters, storing return values, and general computation.
Local Registers: These are context-specific and tied to the current function or interrupt context. Think of them like a fast-access scratchpad that gets swapped in/out depending on what’s running.

This setup is similar in spirit to register windows in SPARC ( traumatic ;) or banked registers in some ARM modes, but Hyperstone does it in its own way. It helps reduce memory access during function calls and interrupt handling, which is great for real-time performance.

How It Works

When a function is called, the CPU switches to a new set of local registers, avoiding the need to push/pop values to the stack. On interrupt, it swaps in a dedicated interrupt register set, so you don’t clobber your working state. The compiler (or hand-written asm) decides what goes into global vs local, but the hardware handles the switching automatically. This means fewer cycles wasted on context switching and more deterministic timing-one of the reasons Hyperstone chips are used in industrial and storage systems where timing matters more than raw speed.

Core Architecture Highlights

Orthogonal instruction set
Big-endian system
Load/store architecture
Variable-length instructions
Separate memory and I/O spaces (both pipelined, two stages)
On-chip memory (16 KB)
On-chip instruction cache (up to 128 bytes) with prefetch logic
Delayed branches
Software instruction ( DO ) and floating-point emulation
Most instructions execute in one cycle

Instruction Set

Memory : LD, ST, MOV, RET
Logical : AND, ANDN, OR, XOR, NOT, MASK
Math : ADD, SUM, SUB, NEG, MUL, DIV
Shift/Rotate : SHL, SAR, SHR, ROL, RR, XM1, XM2, XM4, XM8, XX1, XX2, XX4, XX8
Compare/Test : CMP, CMPB, TESTLZ, CHK, CHKZ
Set : SETADR, SETcc
PC Change: Bcc, DBcc, CALL, TRAPcc, RET
Extended DSP: EMUL, EMAC, EMSUB, EHMAC, EHCMUL, EHCMAC, EHCSUMD, EHCFFT
FPU: FADD, FSUB, FMUL, FDIV, FCVT, FCMP
Other : NOP, FRAME, FETCH, SOFTWARE/DO

cc = condition code

Entry Tables

Entry tables in Hyperstone E1 CPU are placed depending on memory region: for MEM3 they go from top of memory, for other regions from bottom. It’s selected by register config. Trap entry table is separate, also FPU emulation has own entry table.

Trap Instructions

Address A	Address B	Entry	Description	Priority
FFFF FF00	x000 00FC	TRAP 0
FFFF FF04	x000 00F8	TRAP 1
:	:	:
FFFF FFC0	x000 003C	TRAP 48	IO2 Interrupt	15
FFFF FFC4	x000 0038	TRAP 49	IO1 Interrupt	14
FFFF FFC8	x000 0034	TRAP 50	INT4 Interrupt	13
FFFF FFCC	x000 0030	TRAP 51	INT3 Interrupt	11
FFFF FFD0	x000 002C	TRAP 52	INT2 Interrupt	9
FFFF FFD4	x000 0028	TRAP 53	INT1 Interrupt	7
FFFF FFD8	x000 0024	TRAP 54	IO3 Interrupt	5
FFFF FFDC	x000 0020	TRAP 55	Timer Interrupt	6, 8, 10, 12
FFFF FFE0	x000 001C	TRAP 56	Reserved	17
FFFF FFE4	x000 0018	TRAP 57	Trace Exception	16
FFFF FFE8	x000 0014	TRAP 58	Parity Error	4
FFFF FFEC	x000 0010	TRAP 59	Extended Overflow	3
FFFF FFF0	x000 000C	TRAP 60	Range, Pointer, Frame and Privilege error	2
FFFF FFF4	x000 0008	TRAP 61	Reserved	1
FFFF FFF8	x000 0004	TRAP 62	Reset	0
FFFF FFFC	x000 0000	TRAP 63	Error entry for instruction code of all ones

Floating Point Instruction Emulation

FPU emulation uses its own entry table, separate from traps. It handles floating point instructions that CPU doesn’t support natively. When such opcdoe appears, control jumps to emu handler ‘via’ entry table. You can patch or extend it if needed, but it’s not super fast - mostly used when hardware FPU is missing / disabled.

Address A	Address B	Entry	Description
FFFF FE00	x000 01FC	FADD	FP Add, single word
FFFF FE10	x000 01EC	FADDD	FP Add, double word
FFFF FE20	x000 01DC	FSUB	FP Subtract, single word
FFFF FE30	x000 01CC	FSUBD	FP Subtract, double word
FFFF FE40	x000 01BC	FMUL	FP Multiply, single word
FFFF FE50	x000 01AC	FMULD	FP Multiply, double word
FFFF FE60	x000 019C	FDIV	FP Divide, single word
FFFF FE70	x000 018C	FDIVD	FP Divide, double word
FFFF FE80	x000 017C	FCMP	FP Compare, single word
FFFF FE90	x000 016C	FCMPD	FP Compare, double word
FFFF FEA0	x000 015C	FCMPU	FP Compare Unordered, single word
FFFF FEB0	x000 014C	FCMPUD	FP Compare Unordered, double word
FFFF FEC0	x000 013C	FCVT	FP Convert single word to double word
FFFF FED0	x000 012C	FCVTD	FP Convert double word to single word
FFFF FEE0	x000 011C		Reserved
FFFF FEF0	x000 010C	DO	DO instruction

Arcade Paltforms

As mentioned before, in South Korea quite many arcade machines from late 90s and early 2000s were based on Hyperstone CPUs. You can point out at least four hardware platforms - systems that shared same components (mostly video and sound chips). The last one (Semicom) uses both 16 and 32-bit Hyperstone CPUs. Its video hardware (based on sprites) has many variants,but all follow same basic idea.