Introduction
General SOC Info
CPU Core
Memory Map
Control Registers
Graphics Hardware
Sound Generator
M.A.C.S.
Arcade Games

Introduction

All informations here are based only on guessing, reverse engineering and analysis of the games. There’s no public documentation of the ST-0016 available.

So, this documentation is most likely incorrect in many places and missing several key elements. The research of the audio part was done by RB and Haze. The rest is my own work with help from other MAME developers.

General SOC Info

ST-0016 is a SOC - Z80 8 bit CPU core + I/O, graphics and sound hardware in one. It was designed/created by japanese company Seta (Super Entertainment and Total Amusement) probably around 1993 (the earliest made chip we found is dated for 48th week of 1993 (9348YAA). ST-0016 is 208 pin PQFPn( Plastic Quad Flat-Pack) device, probably a Toshiba Gate Array (market as TC6187AF or TC6210AF).

CPU Core

The heart of the ST-0016 system is a processor core compatible with the popular 8-bit Zilog Z80. So far, no differences or enhancements have been identified. Detailed documentation is available on the manufacturer’s website. The processor usually operates in the first interrupt mode (handled at address $38). Several titles also use a non-maskable interrupt handled at $66. The sources of both interrupts are unknown. The INT is likely synchronized with vertical blanking (VBLANK = 60 Hz), while the NMI is triggered either by an external signal or as a result of (internal?) timers (experimentally determined NMI frequency is 15 Hz).

While INT blocking is performed using standard Z80 instructions (di/ei), the method of controlling NMI (at least one game requires blocking this interrupt) remains unknown.

Memory Map

The ST-0016 system is based on a Z80 processor capable of addressing up to 64 KB of memory. However, the user has access to a significantly larger amount of memory. In its basic configuration, the system provides the following RAM blocks:

2 MB of memory known as Character RAM, used to store graphics (characters) and sound samples.
2 KB Palette RAM - stores color information
64 KB Sprite RAM - contains sprite lists
128 B Common RAM + 2 KB RAM + 4 KB WORK RAM

The values listed above are most likely the maximum supported/addressable by the hardware. Some of the memory (likely CHARACTER RAM, WORK RAM, and SPRITE RAM) is located outside the ST-0016 chip in separate modules.

In addition to RAM, the board also includes a significant amount of ROM chips. The exact amount depends on the specific game. For example, Nerrate Chu uses 1.5 MB of ROM, while Srmp5 uses 20 MB.

To enable access to all memory regions, the system employs a memory banking mechanism. Memory is divided into fixed-size blocks (banks), and “windows” in the CPU address space allow specific ROM or RAM regions to be “visible.” This concept is illustrated in the diagram below:

The selection of the memory bank (block) visible in the appropriate window is made by writing its number to the corresponding register of the ST-0016 (described in more detail in the section on registers). Only the first 32 KB are permanently assigned to the zero ROM bank.

Control Registers

In the Seta system, hardware registers are mapped into the I/O space of the Z80 processor.

These can be divided into several groups (addresses are highlighted in bold):

Video/Timer Registers ($00 - $01)

These likely contain the number of the currently displayed video line and/or timer parameters. Several games wait for specific values to appear in these registers.
Tilemap Registers ($08 - $40)

Seven (or eight, possibly registers $00 - $07 are also used) sets of 8 registers each, corresponding to 7 (or 8) tilemaps. The exact function of these registers is unclear, but it is sufficient for proper emulation:

0 - ??? (usually $00/$20/$ba)
1 - tilemap address in Character Ram /$1000 (e.g. 3 -> tilemap at address $3000)(0 = no tilemap)
2 - ??? (usually $ff/$1f/$af)
3 - tilemap - sprite priority (0 - under, $ff - over)
4 - ??? (usually &7f/&ff)
5 - ??? (possibly connected with priority (register no 3 - usually $20 or $29 (when reg 3 = $ff))
6 - ??? (usually 0)
7 - ??? (usually $20/$10/$12)
Scroll Registers ($40 - $60)
Each sprite list can be additionally linked to a pair of registers that shift all its elements on the screen by a specified number of pixels. There are 16 independent pairs of registers (for X and Y coordinates). The shift is a signed 16-bit value and occupies two consecutive registers. For example, the first pair is mapped to addresses $40,$41 for X and $42,$43 for Y.
DMA Registers ($a0 - $a8 oraz $f0)

The ST-0016 includes an integrated DMA controller, allowing for fast data transfers to Character RAM without using the processor.

After loading the appropriate registers with the transfer parameters, setting bit 5 in $a8 initiates data transfer. Once the copying is complete, bits 0 and 1 in register $f0 are cleared.

Memory Control Registers ($e0 - $e6)

$e1 - ROM bank : 00-$ff
$e2 - Sprite RAM bank : upper nibble - BANK 1, lower nibble - BANK 2
$e3 - $e4 - Character RAM bank : 0-$ffff
$e5 - Palette RAM bank : 0-$ffff
The purpose of registers $e0 and $e6 is unknown. Register $e0 is frequently used-for example, Renju writes the value $40 to it, while Neratte writes $0.
Watchdog ($e7)
Unfortunately, it is unknown how often the watchdog must be reset to ensure proper system operation.
I/O ($c0 - $df)
The I/O lines are externally connected from the ST-0016 and are used for communication with other components. Their function depends on the specific implementation. For instance: • In Renju/Neratte, ports $c0-$c3 are used for reading game settings (DSW) and controls. • In games using the V810 processor, ports $c0-$c3 are reserved for communication with that processor, while $d0-$d3 serve a similar purpose as $c0-$c3 in Renju. • The M.A.C.S. system uses the range $c0-$c7 for keyboard input and communication with additional peripherals such as printers or hoppers.

Graphics Hardware

The basic element from which graphics are built in the ST-0016 is the so-called tile (character), a square graphical element with dimensions of 8x8 six-color pixels. Each tile occupies exactly 32 bytes of memory (884 bits, to define 16 colors) – hence the size of the CHARACTER RAM window is 32 bytes. We have access to 1024 colors (R:5, G:5, B:5) grouped into 64 palettes, each with 16 colors (the zero index of the palette points to a transparent pixel). Each tile (both a part of a sprite or a cell from a character map) can use any (one of 64) color palette. Additionally, it is possible to use 256 colors in a single tile. By setting the appropriate bit, we allow the summing of the colors of the current tile and the background color, resulting in a 4+4 = 8-bit value.

The graphics created by the Seta system are based on eight tilemaps and a large number of sprites.

The map parameters are set through the $00-$40 registers of the system (each using 8). Their meaning is described in more detail in the section on registers. The tilemaps are stored in SPRITE RAM – arranged in columns (with a height of 32 cells, though there is likely an option to set the size). Each map element (known as a cell) occupies four bytes. The first two bytes contain the tile number, the next byte contains the palette number, and the fourth byte defines additional parameters (flipx/flipy in bits 6 and 7, respectively).

However, the main focus is placed on sprites. The initial addresses of SPRITE RAM are occupied by a sprite list. This list defines the position and addresses of sprite groups (lists of sprites).

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In addition to the main sprite list (terminated with an element that has an end marker), there are sublists that describe each sprite in detail – its relative position, its vertical and horizontal size (which is a power of 2), the tile numbers used, the color palette, and several additional parameters (such as flipping, merging with previous graphics, etc.).

The actual tile coordinate on the screen is the sum of the tile’s offset in the sprite, the sprite’s local coordinates, the global coordinates (set in the main list), and the offset resulting from the use of specific scroll registers.

Sound Generator

The ST-0016 allows playback of sound samples (stored in CHARACTER RAM) across 8 separate channels. The sound registers are located at addresses $C900 - $C9FF, with 32 bytes allocated for each of the 8 channels. Their function is explained in the diagram below:

The system outputs a two-channel (stereo) data stream, which is then converted into an analog signal by an external DAC (typically the NEC uPD6376 ).

M.A.C.S.

Multi Amenity Cassette System.

As the name suggests, this is a system based on game cartridges. It consists of a motherboard containing the BIOS and the ST-0016 chip (with surface scracthed) and cartridges with games, which are connected to two sockets on the motherboard. The hardware creators took a very unconventional approach to the ROMs containing data. Both on the motherboard (BIOS) and on the cartridges (ROMs), the data is divided into two parts: one containing even bytes and the other containing odd bytes. This is a common solution in 16-bit systems primarily based on Motorola 68k processors. In the case of M.A.C.S., this serves no significant purpose and presumably (similar to the removal of markings on the ST-0016) was intended to “confuse the enemy” (the competition/pirates).

As mentioned in the introduction, M.A.C.S. is a system based on the ST-0016. It was probably created by Seta (several solutions are characteristic of the hardware of this company, including the GAL chip near the cartridge slot), but it is branded by “I’Max” (the earlier (1995-1996) MACS) or ”Yubis / T.System” (the later (1999) MACS 2). In the design of the motherboard (not in the Seta system), however, several significant changes were introduced compared to the solutions used in Renju or Nerrate, which expand the system’s capabilities. Unfortunately, at this moment, there are more unknowns than certainties, which makes accurate emulation of M.A.C.S. impossible. Another obstacle is the exotic nature of the games (mahjong, hanafuda), which prevents thorough testing of the system.

The most important modifications are:

Inputs/outputs prepared for Mahjong/Hanafuda games
Compatibility with hoppers, ticket dispensers, and other similar devices
BIOS + two cartridge slots (each cartridge contains its own ROM and NVRAM)
Significantly more RAM (at least double the WORK RAM)

At any time, access to each memory area is possible (at least one game uses two cartridges). The graphics subsystem (i.e., the ST-0016) also differs slightly from the basic version. A significant portion of the graphical elements (tilemaps, sprites) is vertically flipped (likely utilizing non-emulated features of the Seta system, known as ‘screen flip”) – a similar behavior is observed in the game Mayjinsen. I hope that some of the mysteries of M.A.C.S. will be uncovered after performing an autopsy of the motherboard and cartridge, which I hope to carry out once both elements are in my hands. Currently, we know of 5 games operating on this system – more information can be found in the relevant section above.